Synopsys and TSMC have collaborated to deliver certified design flows for advanced packaging solutions using the Synopsys 3DIC Compiler product for both silicon interposer based Chip-on-Wafer-on-Substrate (CoWoS-S) and high-density wafer-level RDL-based Integrated Fan-Out (InFO-R) designs. 3DIC Compiler provides packaging design solutions required by today’s complex multi-die systems for applications like high-performance computing (HPC), automotive and mobile.

The Synopsys 3DIC Compiler solution provides a unified chip-package co-design and analysis environment for creating an optimal 2.5D/3D multi-die system in a package. The solution includes features such as TSMC design macro support and auto-routing of high-density interposer based interconnects using CoWoS technology. For RDL-based InFO designs, schedules are reduced from months to a few weeks through automated DRC-aware, all-angle multilayer signal and power/ground routing, power/ground plane creation, and dummy metal insertion, along with the support for TSMC design macros.

For CoWoS-S and InFO-R designs, dies need to be analyzed in the context of the package and the overall system.  Die-aware package and package-aware die power integrity, signal integrity, and thermal analysis are critical for design validation and signoff. Integration of Ansys’ RedHawk family of chip-package co-analysis solutions in 3DIC Compiler meets this critical need, enabling seamless analysis and faster convergence to an optimal solution. Customers can achieve smaller designs and higher performance by eliminating overdesign.